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IS31FL3726 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 1 16-bit color led driver with pwm control january 2012 general description the IS31FL3726 is comprised of constant-current drivers designed for color leds. the output current value can be set using an external resistor. the output current value can be adjusted from 5ma to 60ma through the external resistor. as a result, all outputs will have virtually the same current levels. this driver incorporates 16-bit constant t-current outputs, a 16-bit shift register, a 16-bit latch and a 16-bit and-gate circuit. these drivers have been designed using the cmos process. features ? output current capability and number of outputs: 60ma 16 outputs ? constant current range: 5ma to 60ma ? application output voltage: 0.4v ? for anode-common leds ? power supply voltage range, v dd = 3.3v to 5.5v ? serial and parallel data transfer rate: 20mhz (max. cascade connection) ? operating temperature range, t a = ? 40c ~ +85c ? package: qfn-24 ? current accuracy (all output on) applicationas ? cellular phones ? mp3/mp4/cd/minidiskplayers ? toys block diagram figure 1 block diagram output voltage current accuracy output current between bits between ics 0.4v 4% 12% 5 to 60 ma
IS31FL3726 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 2 typical application circuit . . . . . . microcontroller vbat o1 o2 o3 o16 o15 o14 rext gnd serial-in enable latch clock vdd r1 =2 ko hm ( t p y . ) 0.1uf ldo 3.3v figure 2 typical application figure
IS31FL3726 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 3 pin configuration package pin configuration (top view) qfn-24 1 2 3 4 24 14 15 16 17 23 22 21 7 8 9 10 5 11 18 20 6 12 13 19 latch out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 vdd clock gnd serial-in r-ext serial-out out11 out12 out13 out14 out15 enable pin description no pin description 1 serial-out output terminal for serial data input on serial-in terminal. 2 r-ext input terminal used to connect an external resistor. this regulated the output current. 3 vdd supply voltage terminal. 4 gnd gnd terminal for control logic. 5 serial-in input terminal for serial data for data shift register. 6 clock input terminal for clock for data shift on rising edge. 7 latch ???????? input terminal for data strobe when the l a t c h ???????? input is driven high, data is not latched. when it is pulled low data is latched. 8 ~ 23 out0 ?????? ~out15 ??????? constant-current output terminals. 24 enable ????????? input terminal for output enable. all outputs (out0 ?????? to out15 ??????? ) are turned off, when the enable ????????? terminal is driven high .and are turned on, when the terminal is driven low. thermal pad connect to gnd. copyright ? ? ? 2011 ? integrated ? silicon ? solution, ? inc. ? all ? rights ? reserved. ? issi ? reserves ? the ? right ? to ? make ? changes ? to ? this ? specification ? and ? its ? products ? at ? any ? time ? without ? notice. ? issi ? assumes ? no ? liability ? arising ? out ? of ? the ? application ? or ? use ? of ? any ? information, ? products ? or ? services ? described ? herein. ? customers ? are ? advised ? to ? obtain ? the ? latest ? version ? of ? this ? device ? specification ? before ? relying ? on ? any ? published ? information ? and ? before ? placing ? orders ? for ? products. ? integrated ? silicon ? solution, ? inc. ? does ? not ? recommend ? the ? use ? of ? any ? of ? its ? products ? in ? life ? support ? applications ? where ? the ? failure ? or ? malfunction ? of ? the ? product ? can ? reasonably ? be ? expected ? to ? cause ? failure ? of ? the ? life ? support ? system ? or ? to ? significantly ? affect ? its ? safety ? or ? effectiveness. ? products ? are ? not ? authorized ? for ? use ? in ? such ? applications ? unless ? integrated ? silicon ? solution, ? inc. ? receives ? written ? assurance ? to ? its ? satisfaction, ? that: ? a.) ? the ? risk ? of ? injury ? or ? damage ? has ? been ? minimized; ? b.) ? the ? user ? assume ? all ? such ? risks; ? and ? c.) ? potential ? liability ? of ? integrated ? silicon ? solution, ? inc ? is ? adequately ? protected ? under ? the ? circumstances
IS31FL3726 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 4 ordering information industrial range: -40c to +85c order part no. package qty/reel IS31FL3726-qfls2-tr qfn-24, lead-free 2500
IS31FL3726 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 5 n = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 clock serial-in latch enable out0 out1 out2 out15 serial-out h l h l h l h l on off on off on off on off h l figure 3 timing dagram warning: latch circuit is leveled-latch circuit. be careful because it is not triggered-latch circuit. note : the latches circuit holds data by pulling the l a t c h ???????? terminal low. and, when l a t c h ???????? terminal is a high level, latch circuit doesn?t hold data, and it passes from the input to the output. when e n a b l e ????????? terminal is a low level, output terminal o u t 0 ?????? to o u t 1 5 ??????? respond to the data, and on and off does. and, when e n a b l e ????????? terminal is a high level, it offs with the output terminal regardless of the data. truth table clock latch ???????? enable ????????? serial-in out0 ?????? ? out7 ?????? ? out15 ??????? serial-out h l dn dn ?dn-7 ?dn-15 dn-15 l l dn+1 no change dn-14 h l dn+2 dn+2 ?dn-5 ?dn-13 dn-13 x l dn+3 dn+2 ?dn-5 ?dn-13 dn-13 x h dn+3 off dn-13 note : out0 ????? to out15 ????? =on when dn = h; out0 ????? to out15 ????? =off when dn = l. in order to ensure that the level of the power supply voltage is correct, an external resistor must be connected between r-ext and gnd. warning: when v dd < 2.5v or the start up time is less than 1ms, the following conditions, enable ____________ =0, latch __________ =1, serial-in=1, cannot be configured at the same time, or sn3726 will be abnormal.
IS31FL3726 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 6 absolute maximum ratings supply voltage, v dd - 0.3v ~ +6.0v voltage at any input pin - 0.3v ~ v dd +0.2v maximum junction temperature, t jmax 150c storage temperature range, t stg - 65c ~ +150c operating temperature range, t a ? 40c ~ +85c esd (hbm) 3kv note: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating condition t a = 25c, unless otherwise specified. characteristic symbol condition min. typ. max. unit supply voltage v dd 3.3 5.5 v output voltage v out 0.7 4 v output current i out each dc 1 circuit 5 60 ma/ch i oh serial-out -1 ma i ol serial-out 1 input voltage v ih 1.4 v v il 0.4 clock frequency f clk cascade connected 20 mhz latch ???????? pulse width t wlat 50 ns clock pulse width t wclk 25 ns enable ????????? pulse width (note ) t wena upper i out = 20ma 2000 ns lower i out = 20ma 3000 set-up time for clock terminal t setup1 10 ns hold time for clock terminal t hold 10 ns set-up time for l a t c h ???????? terminal t setup2 50 ns note : when the pulse of the low level is input to the e n a b l e ????????? terminal held in the high level.
IS31FL3726 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 7 electrical characteristics t a = 25c, v dd = 3.3v ~ 5.5v, unless otherwise specified. characteristic symbol condition min. typ. max. unit supply voltage v dd normal operation 3.3 5.5 v output current i out1 v out = 0.4v v dd = 3.3v r ext = 1k ? 15 18.7 22 ma i out2 v out = 0.4v v dd = 5v 15 18.9 22 output current error between bits i out1 v out 0.4v, all outputs on r ext = 1k ? 3 4 % output leakage current input voltage i oz v out = 5.0v 1 ua input voltage v ih 1.4 v v il 0.4 sout terminal voltage v ol i ol = 1.0ma, v dd = 3.3v 0.3 v i ol = 1.0ma, v dd = 5v 0.3 v oh i oh = -1.0ma, v dd = 3.3v 3 i oh = -1.0ma, v dd = 5v 4.7 output current supply voltage regulation %/v dd when v dd is changed 3.3v to 5.5v -1 % pull-up resistor r (up) enable ????????? terminal 250 500 750 k ? pull-down resistor r (down) latch ???????? terminal supply current i dd(off)1 v out = 5v r ext = open 1 ma i dd(off)2 v out = 5v all outputs off r ext = 1k ? 4.5 i dd(on)1 v out = 0.7v all outputs on r ext = 1k ? 5
IS31FL3726 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 8 switching characteristics t a = 25c, unless otherwise specified. characteristic symbol condition min. typ. max. unit propagation delay t plh1 clk-outn ?????? , l a t c h ???????? = ?h? enable ????????? = ?l? 80 200 ns t plh2 latch ???????? ?outn ?????? , ena ble ????????? = ?l? 80 200 t plh3 enable ????????? -outn ?????? , l a t c h ???????? = ?h? 130 250 t plh clk-serial out 3 5 t phl1 clk-outn ?????? , l a t c h ???????? = ?h? enable ????????? = ?l? 160 250 t phl2 latch ???????? -outn ?????? , enable ????????? = ?l? 160 250 t phl3 enable ????????? -outn ?????? , l a t c h ???????? = ?h? 200 350 t plh clk-serial out 4 6 output rise time t or 10%~90% of voltage waveform 30 150 200 ns output fall time t of 90%~10% of voltage waveform 150 200 250 ns maximum clock rise time t r when not on pcb note ) 5 us maximum clock fall time t f 5 us conditions: (refer to test circuit.) topr = 25c, v dd =v ih =3.3 v and 5 v, v out = 0.7 v, v il =0 v, r ext =1000 ? ,v l =3.0 v, r l =60 ? , c l =10.5 pf note: 1. if the device is connected in a cascade and tr/tf for the waveform is large, it may not be possible to achieve the timing re quired for data transfer. please consider the timings carefully. 2. delay between outputs. the IS31FL3726 has graduated delay circuits between outputs. the fixed delay time is 5ns (typical), o ut1 has 5ns delay, out2 has 10 ns delay, etc. this delay prevents large inrush currents, which reduce power supply bypass capacitor require ments when the outputs turn on. the delay works during switch on and switch off of each output channel. leds that have not turned on befor e enable ??????? is low will still turn on and off at the determined delayed time regardless of the state of enable ??????? . therefore, every led will be illuminated for the amount of time enable ??????? is pulled high. figure 4 test diagram
IS31FL3726 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 9 timing waveform 1 clock, serial-in,serial-out 2. clock, serial-in, latch ???????? , e n a b l e ?????????? , outn ?????? 3. outn ??????
IS31FL3726 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 10 typical operatin g characteristics adjusting output current the output current of each channel is set by an external resistor r ext , the relationship between i out and r ext is: i out = (v r-ext /r ext )52 the v r-ext is 0.36v in the IS31FL3726,so we can count the i out as : i out = 0.3652/r ext . as show in the figure below: 10 15 20 25 30 35 40 45 50 400 600 800 1000 1200 1400 1600 rset() led current(ma) -40c 25c 85c
IS31FL3726 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 11 classification reflow profiles profile feature pb-free assembly preheat & soak temperature min (tsmin) temperature max (tsmax) time (tsmin to tsmax) (ts) 150c 200c 60-120 seconds average ramp-up rate (tsmax to tp) 3c/second max. liquidous temperature (tl) time at liquidous (tl) 217c 60-150 seconds peak package body temperature (tp)* max 260c time (tp)** within 5c of the specified classification temperature (tc) max 30 seconds average ramp-down rate (tp to tsmax) 6c/second max. time 25c to peak temperature 8 minutes max. figure 5 classification profile
IS31FL3726 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 12 tape and reel information
IS31FL3726 integrated silicon solution, inc. ? www.issi.com rev.a, 12/19/2011 13 package information qfn-24 note: all dimensions in millimeters unless otherwise stated.

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